Conventionally, in the technical field of a plasma display device, there is a known device of a method wherein multiple X electrodes and multiple Y electrodes are mutually adjacently placed in a horizontal direction and address electrodes are placed in a vertical direction to form a matrix so that an image is displayed by applying drive waveforms from an X driving circuit, a Y driving circuit and an address driving circuit to a discharge cell at an intersection of the electrodes.
FIG. 9 shows a schematic diagram of a panel and driving circuits of a conventional plasma display device. FIG. 10 show a structure of a plasma display panel and a subfield configuration of a driving signal.
With reference to FIG. 9, the plasma display device is composed of a plasma display panel 3, an X driving circuit 4, a Y driving circuit 5, an address driving circuit 6 and a control circuit 7.
The X driving circuit 4 applies a drive waveform to multiple X electrodes 11 of the panel 3. The Y driving circuit 5 applies a drive waveform to multiple Y electrodes 12 of the panel 3. The address driving circuit 6 applies a drive waveform to multiple address electrodes 15 of the panel 3. The control circuit 7 controls the entirety.
According to the panel structure of the plasma display described in FIG. 10, the multiple X electrodes 11 and Y electrodes 12, a dielectric layer 13 and a protective layer 14 are placed on the surface of a front plate 1. In addition, the multiple address electrodes 15, a dielectric layer 16, a bulkhead 17 and phosphors 18 to 20 which are orthogonal to the X electrodes 11 and Y electrodes 12 are placed on the surface of a backplane 2. A gas which is a discharge gas is encapsulated in space inside a cell, where a voltage applied to each of the electrodes is controlled so as to discharge electricity by putting the gas in an excited state. The phosphors 18 to 20 convert ultraviolet generated by the discharge to visible light.
The subfield configuration diagram of the driving signal described in FIG. 10 (a) shows the configuration of subfields 21 to 30 having 10 fields. FIG. 10 (b) describes that a reset interval 31, an address interval 32 and a sustain interval 33 are provided in one subfield.
FIG. 11 shows the drive waveforms in the case of resetting all the cells in a write interval within the reset interval of a conventional plasma display panel.
FIG. 11 shows examples of the drive waveforms wherein, as shown in FIGS. 10 (a) and (b) for instance, a field section is divided into multiple subfields, and the subfield is divided into the reset interval, address interval and sustain interval while the reset interval is further divided into the write interval and a charge adjustment interval, and the address interval is divided into an first half address interval and a second half address interval.
As for the drive waveforms in the case of resetting all the cells shown in FIG. 11, a driving voltage applied to the Y electrode increases (changes in a positive direction) from a voltage Vs in the write interval of the reset interval, and the driving voltage applied to the Y electrode decreases (changes in a negative direction) in the charge adjustment interval so as to reach a certain ultimate voltage (−Vy+α).
FIG. 12 shows the drive waveforms in the case of resetting only the cells lit up in the write interval of the reset interval of the conventional plasma display panel.
As for the drive waveforms in the case of resetting only the lit up cells in FIG. 12, the driving voltage applied to the Y electrode is maintained at a fixed value 2Vs in the write interval of the reset interval, and the driving voltage applied to the Y electrode decreases (changes in the negative direction) in the charge adjustment interval so as to reach a certain ultimate voltage (−Vy+α).
FIG. 13 are diagrams showing the Y driving circuit of the conventional plasma display panel and timing between the drive waveform applied to the Y electrode and switching of each individual switch.
The Y driving circuit of FIG. 13 includes positive constant voltages Vs, Vw and negative constant voltages (−Vy+α), (−Vy), and is composed of multiple diodes, multiple inductances L, multiple capacitances C, multiple resistances R and multiple switches SW 1 to SW 13. The Y driving circuit controls the timing of switching (on/off: H, L) of the multiple switches SW 1 to SW 13 so as to apply the drive waveform of the Y electrode to a panel Cpanel.
As for the drive waveform applied to the Y electrode, as shown in FIG. 11, the voltage rises in the first half of the reset interval to reach Vs+Vw, and the voltage lowers in the second half of the reset interval to reach −Vy+α. And a pulse voltage of −Vy is applied to the Y electrode in the address interval. Concurrently with applying the pulse voltage of −Vy to the Y electrode, the pulse voltage of +Va is applied to the address electrode so that the electrical discharge is started between the address electrode and the Y electrode, and the electrical discharge is further performed between the X electrode and the Y electrode so as to address the cells that light up. After that, in the sustain interval, the opposite pulse voltage Vs is alternately applied between the X electrode and the Y electrode so as to continue a sustained discharge.
The following Patent Document 1 discloses a plasma display driving method wherein, in the case where panel temperature rises or the panel lights up for a long time, a pulse for reducing a wall voltage is applied to a scan side electrode immediately before applying a base voltage so as to reduce an electric potential of the scan side electrode for the purpose of curbing deterioration of a display lighting state in the case where the panel temperature rises or the panel lights up for a long time.
FIG. 14 show a schematic diagram of the panel and driving circuit of the plasma display device and the drive waveform applied to each of the electrodes according to Patent Document 1.
In FIG. 14, a panel temperature detection portion detects the panel temperature of the plasma display panel. In the case where panel temperature rises, or the like, the panel temperature detection portion applies a pulse of a negative voltage for lowering the electric potential of the scan side electrode to the scan side electrode immediately before applying a base voltage Vscn so as to prevent the deterioration of the display lighting state in the case where the panel temperature rises or the panel lights up for a long time.
The deterioration of the display lighting state is caused due to unnecessary electrical discharge generated by molecules excited by slightly emitted electrons when a protection film of the panel is sputtered by the electrical discharge during the lighting and impurities in the protection film are emitted in the gas to increase the molecules in the gas in the case where the impurities in the phosphors gasify due to the rise in the panel temperature and increase the molecules in the gas or in the case where the panel is lit up for a long time.
The pulse applies the negative voltage to the scan side electrode for a short period of time immediately before applying the base voltage Vscn and reduces the wall voltage so as to prevent the deterioration.
Patent Document 1: Japanese Patent Laid-Open Publication No. 2003-140601
FIG. 15 show the drive waveform applied to the Y electrode of the conventional plasma display panel and a problem arising in the case of low environment temperature.
In FIG. 15, if there is a rise in the voltage of the drive waveform applied to the Y electrode in the write interval within the reset interval, negative charges accumulate in proximity to the Y electrode in the panel while positive charges accumulate in proximity to the address electrode and the X electrode. The accumulated negative charges and positive charges gradually decrease in the charge adjustment interval. At the time point of a certain ultimate voltage at the end of the charge adjustment interval, the negative charges are accumulated in proximity to the Y electrode in the panel while the positive charges are accumulated in proximity to the address electrode and the X electrode (referred to as “wall charges”).
In the address interval after the reset interval, a positive voltage Va is applied to the address electrode, and a negative voltage −Vy is simultaneously applied to the Y electrode. In the cell where the address electrode intersects with the Y electrode, a potential difference (Va+Vy) between the positive voltage Va and the negative voltage −Vy in the address interval is overlapped in the same direction as the electric potential (wall potential) from the address electrode to the Y electrode due to the wall charges so that the electrical discharge is started. However, there has been a problem that, if the environment temperature of the plasma display becomes low, such as an initial state of power activation in cold climates, there are the cases where generation of a discharge current delays and so the electrical discharge is not finished at the end of the pulse of the positive voltage Va and the negative voltage −Vy in the address interval so that there is high probability of an address error not allowing selection of a luminous cell and it is difficult to secure a stable operation margin.
The invention described in Patent Document 1 detects the panel temperature and changes the voltage of a scan pulse, and particularly applies a short-period pulse immediately before applying the base voltage in order to prevent unnecessary electrical discharge due to increase in the molecules in the gas in the case where the panel temperature rises or the panel is lit up for a long period of time. However, the technique described in Patent Document 1 cannot solve the problem in the case where the environment temperature of the plasma display becomes low.
The problem to be solved by the present invention is the problem that, in the case where the environment temperature of the plasma display is low, the generation of a discharge current delays and the probability of an address error becomes high so that it is difficult to secure a stable operation margin.